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The TMM9200_B SOC is designed to provide a cost-effective, low power and high performance Application Processor solution for MP4 Players and Digital Photo Frames. To reduce the total system cost and enhance the overall functionality of the system,TMM9200_B integrates the functions such as an advanced Audio/ Video decoder, and a control CPU with 16KB/16KB instruction/ data separated caches. In addition it supports various interfaces such as USB2.0 OTG, USB1.1 HCI, LCD, TCON, BT656, ATAPI, IIC, IIS, IR, SPI, SPDIF OUT, general purpose I/O Ports, 2-channel UART with handshake, DVB-T I/F, 12-bit ADC for Touch-screen, 2-channel Voice ADC, 1-channel 10-bits Video DAC, 6-channel Timer with PWM, Stereo 14-bit audio DAC (Class-AB) out, and three PLLs for clock generation.
 
 RISC Processor Architecture
  - ARM926EJ-S based core processor
  - 16-/ 32-bit RISC architecture
 Cache Memory
  - Supports 64 way set-associative cache with I-cache (16KB) and D-cache (16KB)
  - Supports 8-word per line with one valid bit and two dirty bits per line
  - Supports Pseudo random or round robin replacement algorithm
 Memory Controller
  - Supports 1-/2-bit serial flash interface.
  - Supports NAND flash interface
  - Supports 16-/32-bit data bus width for SDRAM interface
 JPEG Decoder
  - Decoded ITU-T.81 (ISO/IEC 10918-1) compliant baseline process.
  - Decodes up to maximum 65535x65535 pixel size
  - Supports variable JPEG image chroma format
  - Supports Fine zoom operation with small memory (under 1MB)
 Multi-Format Video Decoder
  - Decodes MPEG1, MPEG2, MPEG4, H.264, VC-1, RV, and video stream
  - Error resilience tools and multiple decoding simultaneously
  - Decodes images with HD size
 Audio Stream Decoder
  - Decodes MPEG1, MPEG2, OGG, AAC and WMA.
  - Supports down mix
 LCD I/F
  - Horizontal maximum size: 1366 , Vertical maximum size: 768
  - Supported MCU Interface
 12-bit ADC and Touch Screen I/F
  - Resolution: 12-bit
  - Maximum conversion rate: 1MSPS